1. Field of Invention
The present invention relates to a timing control method. More particularly, the present invention relates to a timing control method for operating a synchronous memory.
2. Description of Related Art
In the past ten years or so, there has been some tremendous progress in the operating speed and capacity of memory array. Due to the multiplicity of functions, memory has become one of the principle products in the integrated circuit industry. Memory has developed from the earlier version of non-synchronous memory such as page mode, extended data output (EDO), and pulse extended data output (PEDO) to synchronous memory including synchronous dynamic random access memory (SDRAM), direct random access memory bus dynamic random access memory (direct RAMBUS DRAM), double data rate synchronous dynamic random access memory (DDR-SDRAM), and synchronous linked dynamic random access memory (SLDRAM).
FIG. 1 is a block diagram showing a first type of conventional timing system for a synchronous memory. As shown in FIG. 1, a decoder 102 decodes the system address value Xaddress into an address value Baddress, and a column select signal (CSL) corresponding to the address Baddress changes from a low level to a high level. Thereafter, a piece of local data (LD) is read out from a location in the memory array 104 corresponding to the address value Baddress. Because the signal level of the local data is relatively small (generally has a differential level of around 100 mV), the signal level of the local data must be amplified to a range between 0V and the operating voltage level. Hence, the local data read from the memory array 104 is transferred to a sense amplifier 106 via a local data bus 110. The sense amplifier 106 transforms the received local data signal level into a global data (GD), which is a signal having a range between 0V and the operating voltage level. The global data is then transferred to a register 108 via a global data bus 112 for temporary storage. The global data resides within the register 108 until the next time when the signal triggers the register 108 to output an output data DO to a synchronous memory 100 via an external bus (not shown).
The aforementioned actions are completed in three synchronous timing cycles P0, P1 and P2. FIG. 2 is a timing diagram showing the actions and timing of various signals applied to the synchronous memory in FIG. 1. As shown in FIG. 2, the P0th clock of the synchronous timing xclk initiates the reading of the ath address value Xaddress. The decoder 102 conducts a decoding operation that a column select signal (CSLa) then issues a high level signal and then the memory array 104 reads out the ath batch of local data (LD) from a location corresponding to the address.
A local data bus pre-charge (LDB pre-charge) signal terminal submits a low-level signal to pre-charge the local data bus 110 up to an operating voltage. In the meantime, a global data bus pre-charge (GDB pre-charge) signal terminal also submits a low-level signal to pre-charge the global data bus 112 up to the operating voltage. After pre-charging the local data bus 110 (that is, the LDB pre-charge signal changes from a low level to a high level), the ath batch of local data (LD) in the local data bus gradually changes from signals having a low differential to having a high differential. Similarly, after pre-charging the global data bus 112 (that is, the GDB pre-charge signal changes from a low level to a high level), the sense amplifier 106 amplifies the signal variation of the ath batch of local data into the ath batch of global data. The signal levels now range between 0V and the operating voltage. Thereafter, the sense amplifier 106 transfers the ath batch of global data (GD) to the global data bus 112.
Operations including the decoding of data by the decoder 102, the reading of data from the memory array 104, the pre-charging of the sense amplifier 106, the local data signal developing, the amplification of signals, and the transmission of data are all done within the P0th clocking cycle. In addition, the time period, between the transition of the signal ‘LDB pre-charge’ from a low level to a high level and the transition of the ‘set’ signal from a low level to a high level, which is used to form up a high-low differential for the signals in the ath batch of local data (LD) is also referred to as a signal developing time.
The P1th clocking of the synchronous timing xclk initiates the reading of the (a+1)th address value Xaddress followed by decoding a high level signal submitted to the column select signal (CSL a+1). Thereafter, the (a+1)th batch of local data (LD) is read from a location having the corresponding address. The local data bus 110 and the global data bus 112 are pre-charged. Signal level of the (a+1)th batch of LD is amplified to form the (a+1)th batch of global data (GD) and moreover the (a+1)th batch of GD is transmitted to the global data bus 112. In the meantime, the register 108 stores up the ath batch of GD (Gda as shown in FIG. 2) on the global data bus 112. In other words, the register 108 performs a data registering operation in the P1th clocking cycle.
Similarly, the P2th clocking of the synchronous timing xclk initiates the reading of the (a+2)th address value Xaddress followed by decoding a high level signal submitted to the column select signal (CSL a+2). Thereafter, the (a+2)th batch of local data (LD) is read from a location having the corresponding address. The local data bus 110 and the global data bus 112 are pre-charged. Signal level of the (a+2)th batch of LD is amplified to form the (a+2)th batch of global data (GD), and the (a+2)th batch of GD is transmitted to the global data bus 112. The register 108 stores up the (a+1)th batch of GD (Gda+1 as shown in FIG. 2) on the global data bus 112. In the meantime, the register 108 outputs the previously stored ath batch of GD via an external bus (not shown) connected to the synchronous memory 100 serving as the ath batch of output data DO (indicated by DOa in FIG. 2). In other words, the register 108 conducts a data output operation in the P2th clocking cycle.
FIG. 3 is a block diagram showing a second type of conventional timing system for a synchronous memory. The functions of the components shown in FIG. 3 are very similarly to the ones in FIG. 1. One major difference is that the three synchronous clocking cycles correspond in position to the devices within the synchronous memory. In other words, the operating conditions of the devices in each synchronous cycle are different. FIG. 4 is a timing diagram showing the relationship of various signals acting on the system in FIG. 3.
As shown in FIG. 4 (refer to FIG. 3), the P0th clocking of the synchronous timing xclk initiates the reading of the ath address value Xaddress. The decoder 102 conducts a decoding operation. In other words, the decoder 102 performs a decoding operation in the P0th clocking cycle.
The P1th clocking of the synchronous timing xclk initiates the reading of the (a+1)th address value Xaddress followed by decoding a high level signal submitted to the column select signal (CSLa). At the same time, the memory array 104 reads the ath batch of local data (LD) from a location having the corresponding address. The LDB pre-charge terminal issues a low-level signal so that the signal level of the local data bus 110 is pre-charged to an operating voltage. The GDB pre-charge terminal also issues a low-level signal so that the signal level of the global data bus 112 is pre-charged to the operating voltage.
After pre-charging the local data bus 110 (that is, the LDB pre-charge signal changes from a low level to a high level), the ath batch of local data (LD) in the local data bus gradually changes from signals having a low differential to having a high differential. Similarly, after pre-charging the global data bus 112 (that is, the GDB pre-charge signal changes from a low level to a high level), the sense amplifier 106 amplifies the signal variation of the ath batch of local data into the ath batch of global data. The signal levels now range between 0V and the operating voltage. Thereafter, the sense amplifier 106 transfers the ath batch of global data (GD) to the global data bus 112.
Operations including the reading of data from the memory array 104, the pre-charging of the sense amplifier 106, the local data signal developing, the amplification of signals, and the transmission of data are all done within the P1th clocking cycle. In addition, the time period, between the transition of the signal ‘LDB pre-charge’ from a low level to a high level and transition of the ‘set’ signal from a low level to a high level, which is used to form up a high-low differential for the signals in the ath batch of local data (LD) is also referred to as a signal developing time.
Similarly, the P2th clocking of the synchronous timing xclk initiates the reading of the (a+2)th address value Xaddress followed by decoding. Thereafter, the (a+1)th batch of local data (LD) is read from a location having the corresponding address. A high level signal is submitted from the column select signal (CSL) terminal. The local data bus 110 and the global data bus 112 are pre-charged. Signal level of the (a+1)th batch of LD is amplified to form the (a+1)th batch of global data (GD), and the (a+1)th batch of GD is transmitted to the global data bus 112. The register 108 stores the ath batch of GD on the global data bus 112 and outputs the stored ath batch of GD via an external bus (not shown) connected to the synchronous memory 100 serving as the ath batch of output data DO (indicated by DOa in FIG. 4). In other words, the register 108 conducts a data storage and output operation in the P 2th clocking cycle.
In brief, the sense amplifier needs to complete operations including the pre-charging of the local data bus, timing required for developing local data signals, and the transmission of global data to the global data bus within one clocking cycle. Other devices within the synchronous memory must also complete all their operations within a clocking cycle. Therefore, each device within the synchronous memory gauges each synchronous cycle smoothly so optimization of the clocking cycle is difficult. Ultimately, operating speed of the synchronous memory is constrained. In addition, the signal developing time for local data is fixed, the design margin of the local data developing also suffer operating speed, and hence trying to improve the operating speed of synchronous memory through a minimization of the signal development time is more difficult.